Batch thermal processing continues to be used for several stages of fabrication of silicon integrated circuits. One low temperature thermal process deposits a layer of silicon nitride by low pressure chemical vapor deposition (LPCVD), typically using chlorosilane and ammonia as the precursor gases at temperatures in the range of about 700° C. In one application, about 100 nm of nitride is deposited each cycle on all the wafers in the oven. Similar processes are used for depositing polysilicon and silicon oxyntride. Other, high-temperature processes include oxidation, annealing, silicidation, and other processes typically using higher temperatures, for example above 1000° C. or even 1350° C.
For large-scale commercial production, vertical furnaces and vertically arranged wafer towers supporting a large number of wafers in the furnace are typically used, often in a configuration illustrated in the schematic cross-sectional view of FIG. 1. A furnace 10 includes a thermally insulating heater canister 12 supporting a resistive heating coil 14 powered by an unillustrated electrical power supply. A bell jar 16, typically composed of quartz, includes a roof and fits within the heating coil 14. An open-ended liner 18 fits within the bell jar 16. A support tower 20 sits on a pedestal 22 and during processing the pedestal 22 and support tower 20 are generally surrounded by the liner 18. It includes vertically arranged slots for holding multiple horizontally disposed wafers to be thermally processed in batch mode. A gas injector 24 is principally disposed between the liner 18 has an outlet on its upper end for injecting processing gas within the liner 18. An unillustrated vacuum pump removes the processing gas through the bottom of the bell jar 16. The heater canister 12, bell jar 16, and liner 18 may be raised vertically to allow wafers to be transferred to and from the tower 20, although in some configurations these elements remain stationary while an elevator raises and lowers the pedestal 22 and loaded tower 20 into and out of the bottom of the furnace 10.
The bell jar 18, which is closed on its upper end, tends to cause the furnace 10 to have a generally uniformly hot temperature in the middle and upper portions of the furnace. This is referred to as the hot zone in which the temperature is controlled for the optimized thermal process. However, the open bottom end of the bell jar 18 and the mechanical support of the pedestal 22 causes the lower end of the furnace to have a lower temperature, often low enough that the thermal process such as chemical vapor deposition is not effective. The hot zone may exclude some of the lower slots of the tower 20.
Conventionally in low-temperature applications, the tower, liner, and injectors have been composed of quartz or fused silica. However, quartz towers and injectors are being supplanted by silicon towers and injectors. One configuration of a silicon tower available from Integrated Materials, Inc. of Sunnyvale, Calif. is illustrated in the orthographic view of FIG. 2. It includes silicon bases 30, 32 bonded to three or four silicon legs 34 having slots formed therein to support multiple wafers 38. The shape and length of the fingers between the slots varies with the application and process temperature. The fabrication of such a tower is described by Boyle et al. in U.S. Pat. No. 6,455,395. Silicon injectors are also available from Integrated Materials, as disclosed by. Zehavi et al. in U.S. patent application Ser. No. 11/177,808, filed Jul. 8, 2005 and published as U.S. patent application publication 1006/1085589. Silicon liners have been proposed by Boyle et al. in U.S. Pat. No. 7,137,546.
The height of the tower can be modified according to the height of the furnace and may include slots for over 100 wafers. Such a large number of wafers has prompted the use of thermal buffer wafers and dummy wafers to assure that the production wafers are subjected to a uniform thermal environment within the hot zone. Both the top and the bottom of the stack of wafers in the tower during thermal process are subject to thermal end effects. Particularly, the bottom wafers are heated to a significantly lower temperature and the temperature may be low enough that the nitride CVD process or other thermal process is inactive. Accordingly, thermal baffle wafers rather than the substantially monocrystalline silicon production wafers are placed in the topmost and bottommost slots to thermally buffer the ends of the stack and provide a more uniform temperature distribution for the production wafers placed in between. Often, the pedestal 22 is configured to accept baffle wafers, which are left in the oven throughout many cycles. The thermal baffle wafers also act to scavenge impurities from the furnace ambient that tend to be more populous in the top and bottom of the furnace. It is not uncommon to use up to six or twelve thermal baffle wafers on each end. The baffle wafers may be reused for multiple cycles, but current baffle wafers are typically limited to no more than four or five cycles.
Silicon production wafers are often processed in batches of about 25 wafers, corresponding to the capacity of carrying cassettes transporting them between fabrication tools. The large number of wafer slots allows multiple batches to be simultaneously processed. However, there are situations when less than the maximum number of batches need thermal processing. These situations include process development in the laboratory and process calibration using test wafers every so often on the production. Nitride deposition tends to be sensitive to loading of the oven. That is, the process changes if not all wafer slots are filled. In these situations it is common to nonetheless fully populate the tower by inserting dummy wafers in the empty slots. Polysilicon deposition is subject to somewhat similar loading. On the other hand, oxidation tends to be relatively insensitive to loading.
Dummy wafers and the baffle wafers at the top of the oven on the upstream side of the flow of process gas need to be guarded against production of excessive particles because of film buildup. That is, every so many cycles, they need to be replaced with either fresh dummy and baffle wafers or refurbished ones. On the other hand, the baffle wafers at the bottom of the oven may still create particles but those particles tend not to affect the upstream production wafers.
Dummy and baffle wafers will be collectively referred to as non-production wafers.
Thermal buffer wafers and dummy wafers will be jointly referred to as non-production wafers.
In the past in conjunction with quartz towers, the non-production wafers were typically composed of quartz (fused silica), which are inexpensive and have the further advantage of being opaque to infrared radiation to thereby reduce the end effects of radiation greater than 4.5 μm (the transmissive edge for quartz) bathing the tower. However, just like quartz towels, quartz buffer and dummy wafers have been recognized to contribute to the generation of particles to a degree unsatisfactory for the fabrication of advanced devices. Production types of monocrystalline silicon wafers used as non-production wafers have not been completely successful. They have been observed to fracture easily in repeated use. Further in nitride deposition process, the silicon nitride is deposited on the non-production wafers to greater thicknesses in multiple uses and has been observed to flake off, again creating a particle problems. As a result, in advanced production monocrystalline silicon non-production wafers are limited to a lifetime of only a few cycles before they are discarded or refurbished.
Monocrystalline silicon wafers are currently used as dummy wafers. They closely resemble production wafers except that they may be formed from lesser grade silicon. They have not proved completely satisfactory. In one application for depositing LPCVD silicon nitride, it has been found necessary to replace them after they have accumulated about 330 nm of nitride because they begin shedding particles above this film thickness. Since some applications may be depositing 110 nm of nitride per cycle, the thickness limitation means that the dummy wafers need to be removed every three cycles or so. It is common to reclean the dummy wafers and resuse them. However, only two recleanings are typically performed because the monocrystalline wafers seem to develop streaks on further recleaning. Accordingly, after about 330 nm of nitride or three cycles, the dummy wafers are discarded.
Silicon carbide non-production wafers have also been used, particularly at higher temperatures. However, silicon carbide wafers, especially bulk silicon carbide grown by CVD, are expensive and are also subject to effects arising from the differential coefficient of thermal expansion between a silicon carbide wafer and a silicon tower.
Accordingly, less expensive non-production wafers are desired which nonetheless provide superior performance including ruggedness and ability to have greater thicknessdx of nitride and other material deposited thereon without flaking.